Overview

The PCnet99 JTAG controller consists of one industry standard TAP controller integrated together with a user definable JTAG register array block. The TAP controller is responsible for generating the standard clock and control signals for the Boundary-Scan related operations, while the register array contains various instruction and data registers. Figure 2-1 gives the conceptral view of the JTAG controller.

 

Features of the JTAG Controller include:

• Industry standard TAP controller interface signals.
• A five-bit Instruction Register.
• An external Boundary-Scan register chain.
• A MBIST instruction to perform the built-in self-test.
• An SCANTEST instruction to enable the ATPG scan-chain test.

Block Diagram of Sub-blocks

Figure 2-3 shows the logical block diagram. The JTAG consists of one TAP controller and a few registers. There is only one instruction register. The data register can have different number of registers depending on the user requirement.